This invention relates to programmable logic resources. More particularly, this invention relates to providing more flexible connectivity between signaling input-output (I/O) and an intellectual property block in a programmable logic resource.
Programmable logic resource technology is well known for its ability to allow a common hardware design (embodied in an integrated circuit) to be programmed to meet the needs of many different applications. Known examples of programmable logic resource technology include programmable logic devices (PLDs), complex programmable logic devices (CPLDs), erasable programmable logic devices (EPLDs), electrically erasable programmable logic devices (EEPLDs), and field programmable gate arrays (FPGAs).
A programmable logic resource is typically embedded on a silicon chip that sits in a package containing pins. The programmable logic resource has signaling I/O ports along the periphery of the programmable logic resource that allows data to be received from and transmitted to the pins on the package. The package is typically mounted on a circuit board, which allows for the programmable logic resource to communicate with circuitry external to the package. The circuit board contains wiring that connects the pins to other components on the circuit board.
To facilitate the use of programmable logic resources in certain applications, intellectual property (IP) blocks are coupled to programmable logic resource core circuitry. Data from circuitry external to the package is typically sent to a programmable logic resource through a particular pin and to a corresponding I/O port where the data is decoded and sent to a corresponding data port in the IP block for processing. Similarly, data from the IP block is typically sent to circuitry external to the package through a data port to a corresponding I/O port where the data is encoded and sent to a corresponding pin for output.
During the design stage of a programmable logic resource, a user may not know the size of the programmable logic resource. Often during the same time, a board vendor will design a circuit board having fixed pin connections that support a particular package in which a programmable logic resource is to be located. Because the circuit board is designed with fixed pin connections, the resulting programmable logic resource will be placed in the particular package for which the circuit board is designed to support. However, with different possible sizes of programmable logic resources, the locations of the I/O ports and corresponding data ports at the IP block of the programmable logic resource may change relative to the pin locations for a given package, thereby causing connectivity problems. The data ports in the IP block cannot be easily reconfigured so that the data ports and corresponding I/O ports are matched up with the correct pins without incurring additional costs. In addition, the circuit board cannot be easily rewired so that the pins are matched up with the correct I/O ports and corresponding data ports without incurring additional costs. As a result, extra wiring is typically used to route data between a particular pin to a corresponding I/O port. However, this extra wiring can be limited by the available space for the extra wiring, can cause additional delay times, and can cause further connectivity problems.
In view of the foregoing, it would be desirable to provide more flexible connectivity (i.e., vertical migration) between signaling I/O and an intellectual property block in a programmable logic resource.